1. Field of the Invention
The present invention relates to a substrate treating method including a rinse step of supplying a rinse liquid to a substrate. Examples of substrates to be treated include a semiconductor wafer, a liquid display device substrate, a plasma display substrate, an FED (Field Emission Display) substrate, an optical disk substrate, a magnetic disk substrate, a magnetooptical disk substrate, and a photomask substrate. The present invention relates also to a method of manufacturing a semiconductor device using the substrate treating method.
2. Description of Related Art
For a gate insulating film of a field effect transistor (FET), silicon oxide has been conventionally used. To shrink the size of an element (or device) and highly integrate the same, it is necessary to reduce the thickness of the gate insulating film and secure sufficient on currents. However, rendering thin the gate insulating film made of silicon oxide has nearly reached its limit, and for a device of a technological generation in which a design rule is 32 nm, it is not possible to apply the oxide-silicon gate insulating film. This is because if an silicon oxide gate film having a film thickness of several atom layers is used, a leakage current due to the quantum tunneling effect increases.
Therefore, it has been considered to introduce a gate structure using a so-called High-k material, which is a high dielectric constant material of which the dielectric constant is higher than that of the silicon oxide. When such High-k material is applied to the gate insulating film, the film thickness can be increased to decrease the leakage current, and also a large amount of current can be flown similar to a case where a thin oxide-silicon gate insulating film is used.
A specific gate structure includes an interfacial oxide film formed on a silicon substrate surface, a High-k gate insulating film formed on the interfacial oxide film, and a gate metal (conductor film) formed on the High-k gate insulating film, for example. The interfacial oxide film is made of silicon dioxide. The interfacial oxide film suppresses a reduction in mobility μ due to a High-k gate insulating film, and improves the coating quality of High-k gate insulating film made of hafnium-coating material. As the High-k material, a hafnium-based material is expected to be the most suitable material. For the gate metal, titanium nitride and a tantalum-based material are selected in many cases. These gate metal materials have an intermediate value in work function, and thus, these are suitable materials when forming a CMOS (Complementary Metal Oxide Semiconductor) structure. This is because these materials can be commonly applied to N-channel MOSFET and P-channel MOSFET gate metals. When the gate metal materials are used in common, N-channel and P-channel MOSFET gate structures can be formed simultaneously at a common dry etching step.
The gate insulating film may be configured by a laminate film of a host High-k film having a large film thickness and a cap layer (High-k cap) having a small film thickness. The host High-k film is formed of a hafnium-based material, for example. The cap layer is formed to make contact with the host High-k film, and is made of a metal oxide film such as a lanthanum oxide, a magnesium oxide, or an aluminum oxide.
At an activation annealing step for forming source and drain regions, metal molecules within the cap layer are diffused to the host High-k film. Thereby, a threshold voltage can be shifted, and thus, a desired threshold voltage can be obtained. For example, when an N-channel MOSFET is formed, a cap layer is formed of a material having a work function approximate to that of N-type polysilicon. Likewise, when a P-channel MOSFET is formed, the cap layer is formed of a material having a work function approximate to that of P-type polysilicon. Thereby, the threshold voltages of the MOSFETs can be lowered.
Therefore, when the CMOS structure is formed, a cap layer formed of a material having a work function close to that of N-type polysilicon may be formed on the N-channel MOSFET side, and a cap layer formed of a material having a work function close to that of P-type polysilicon may be formed on the P-channel MOSFET side. Thereby, the threshold voltages of the respective P-channel and N-channel MOSFETs can be lowered while forming the gate metals of a common material.
Specifically, for the cap layer applied to the N-channel MOSFET (hereinafter, referred to as an “N-side cap layer”), a lanthanum oxide or a magnesium oxide having a low work function may be used. For the cap layer applied to the P-channel MOSFET (hereinafter, referred to as a “P-side cap layer”), an aluminum oxide having a high work function can be applied.